Advanced packaging is the frontier of semiconductor technology, and TSMC is in the lead
It’s becoming difficult to make microchips smaller, so the encasing around them is where advanced tech is going. TSMC's advanced packaging technology has emerged as a game-changer, with repercussions extending far beyond circuitry for U.S.-Taiwan relations.
Taiwan Semiconductor Manufacturing Company (TSMC) manufactures the world’s most advanced microchips. The company is not resting on its laurels: In a September 6 talk at the Semicon Taiwan industry conference, TSMC Chairman Mark Liu (劉德音 Liú Déyīn) confirmed the company’s aggressive expansion of its Chip-on-Wafer-on-Substrate (or “CoWoS”) manufacturing capacity, a move set to redefine the strategic landscape of the industry.
“Advanced packaging” is something you are going to be hearing about a lot in the near future. It’s the architecture that links, encases, and safeguards minuscule silicon chips, thus creating the ideal stable operation systems needed for smarter artificial intelligence (AI) devices and other high-end uses. (It’s worth noting that packaging was historically considered a less prestigious, blue-collar task, which led to its migration from the U.S. to Southeast Asia, China, and Taiwan.)
Moore’s Law — formulated in 1965 by Gordon Moore, a co-founder of Intel, states that the number of transistors on a microchip doubles about every two years. But the law isn’t working anymore, and it’s getting more and more difficult to shrink microchips. That’s where advanced packaging comes in: The encasing around the microchips is becoming key to high performance. As the features on semiconductors have decreased to impossibly small dimensions, chip designers have turned to these advanced packaging techniques to improve processor performance without having to further shrink chips’ transistors.
CoWoS, a specific type of advanced packaging, was developed by TSMC to manufacture computing chips like Nvidia’s top-of-the-line A100 and H100, powering a host of AI applications like ChatGPT. Notably, as of today, CoWoS manufacturing does not exist in the U.S.
CoWoS technology sidesteps Moore’s law by allowing multiple chiplets to be packed into one package, dramatically increasing performance and efficiency and reducing energy consumption, all while solving the technical issues that plague current multi-chip arrangements.
Currently, TSMC can’t produce enough CoWoS chips to meet demand, Liu said at Semicon, but the shortage should be alleviated in one and a half years thanks to plans for expanded production.
Liu’s comments highlighted the critical role of semiconductor technology in the age of AI, where tech mastery directly correlates to geopolitical sway. Liu described the journey of semiconductor technology as walking through a tunnel for the past 50 years, focusing on the singular task of shrinking transistors. “Now we are reaching the exit of this tunnel,” he said, emphasizing that while the technology becomes harder to develop, “many more possibilities lie ahead in the future.”
TSMC’s commitment to staying ahead of the competition when it comes to cutting-edge manufacturing comes as the company makes major investments in chip foundries in the U.S. At a time when tech plays a critical role in U.S.-China competition, the success or failure of TSMC’s investments — in advanced packaging and in the U.S. — will take on major geopolitical significance.
TSMC’s vision
Rapid innovation is the norm in the semiconductor industry. But TSMC’s forward-thinking strategies stand out. The company initiated its advanced packaging programs like CoWoS back in 2009, led by Shang-Yi Chiang (蔣尚義 Jiǎng Shàngyì), in anticipation of the technological barriers that could hinder the growth of AI applications, but a long time before it was obvious that packaging would become key to the future of semiconductors.
As a result, TSMC’s CoWoS technology plays a critical role in the manufacturing of AMD’s Instinct MI300 advanced chiplets, and Nvidia’s decision for its H100 manufacturing keeps them uniquely dependent on TSMC, as it is the only firm capable of achieving high-volume manufacturing of such designs at a reasonable cost. Therefore, Nvidia and AMD together account for a significant portion of TSMC’s CoWoS production capacity.
But they’re not the only ones; CoWoS is especially popular for chips that need intense computational power, like those used for AI. Other industry heavyweights like Microsoft’s Athena, Amazon’s Trainium, Google’s TPU, and Intel’s NNP-T also demand CoWoS technology.
Continued investments in chip manufacturing will not only make AI applications more feasible but also exponentially amplify their potential impact across various sectors. Consider the healthcare industry, where AI-driven diagnostics and personalized treatment plans could become more precise and affordable, or national security, where real-time data analytics could offer actionable insights during critical missions. As monolithic chip development faces increasing difficulties, CoWoS represents a pivot to advanced packaging, which industry leaders like AMD’s Lisa Su (蘇姿丰 Sū Zīfēng) have already championed.
This innovation represents more than just a reconfiguration in semiconductor architecture; it introduces a pivotal element that could stir U.S.-Taiwan relations. The evolving situation underscores the United States’ intensified efforts to attract Taiwan’s advanced semiconductor capabilities, including CoWoS, to its shores. Failure to handle these negotiations with delicacy and mutual respect could result in the U.S. missing a seminal opportunity.
As TSMC expands its investments in the U.S., the nexus of cutting-edge CoWoS technology, diplomatic finesse, and corporate interests is shaping a transformative geopolitical landscape that demands close attention.
